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ADT7468
Generating SMBALERT Interrupts from THERM Timer
Events
THERM
The ADT7468 can generate SMBALERTs when a programma-
ble THERM timer limit has been exceeded. This allows the
system designer to ignore brief, infrequent THERM assertions
while capturing longer THERM timer events. Register 0x7A is
THERM
TIMER
(REG. 0x79)
THERM
0 0 0 0 0 0 0 1
7 6 5 4 3 2 1 0
THERM ASSERTED
≤ 22.76ms
the THERM timer limit register. This 8-bit register allows a
limit from 0 secs (first THERM assertion) to 5.825 secs to be set
before an SMBALERT is generated. The THERM timer value is
ACCUMULATE THERM LOW
ASSERTION TIMES
compared with the contents of the THERM timer limit register.
If the THERM timer value exceeds the THERM timer limit
value, then the F4P bit (Bit 5) of Status Register 2 is set and an
SMBALERT is generated. Note that the F4P bit (Bit 5) of Mask
THERM
TIMER
(REG. 0x79)
THERM
0 0 0 0 0 0 1 0
7 6 5 4 3 2 1 0
THERM ASSERTED
≥ 45.52ms
Register 2 (Reg. 0x75) masks out SMBALERTs if this bit is set to
1, although the F4P bit of Interrupt Status Register 2 stays set if
ACCUMULATE THERM LOW
ASSERTION TIMES
the THERM timer limit is exceeded.
THERM
TIMER
(REG. 0x79)
0 0 0 0 0 1 0 1
7 6 5 4 3 2 1 0 THERM ASSERTED ≥ 113.8ms
(91.04ms + 22.76ms)
Figure 31.Understanding the THERM Timer
Figure 32 is a functional block diagram of the THERM timer,
limit, an d associated circuitry. Writing a value of 0x00 to the
THERM timer limit register (Reg. 0x7A) causes SMBALERT to
be generated on the first THERM assertion. A THERM timer
limit value of 0x01 generates an SMBALERT, once cumulative
THERM assertions exceed 45.52 ms.
2.914s
1.457s
728.32ms
2.914s
1.457s
728.32ms
THERM LIMIT
364.16ms
364.16ms THERM TIMER
(REG. 0x7A)
182.08ms
91.04ms
45.52ms
22.76ms
0 1 2 3 4 5 6 7
7 6 5 4 3 2 1 0
182.08ms
91.04ms
45.52ms
22.76ms
(REG. 0x79)
THERM
THERM TIMER CLEARED ON READ
COMPARATOR
IN
OUT
F4P BIT (BIT 5)
STATUS REGISTER 2
SMBALERT
LATCH
RESET
CLEARED
ON READ
1 = MASK
F4P BIT (BIT 5)
MASK REGISTER 2
(REG. 0x75)
Figure 32. Functional Block Diagram of THERM Monitoring Circuitry
Rev. 3 | Page 26 of 81 | www.onsemi.com
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